ICS9148-13 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUMTM

ICS9148 - 13
Pin Descriptions
PIN NUMBER PIN NAME TYPE
DESCRIPTION
1, 2
REF1, REF2
3, 10, 18, 24,
30, 35, 43, 44
4
5
6
7, 26, 27
11,12,13,14,16, 17
19
GND
X1
X2
VDD
FS (0:2)
BUS (1:6)
SS_EN#
20
SS_TYPE
15, 21, 28, 31, 32,
40, 46, 48
22
23
VDD
24MHz
48MHz
25
N/C
29
OE
33, 34, 36, 37, 38,
39, 41, 42, 45, 47, 8, CPU (1:12)
9
OUT 14.318 MHz reference clock outputs.
PWR
IN
OUT
PWR
IN
OUT
IN
IN
PWR
OUT
OUT
IN
OUT
Device Ground
Crystal or external clock input.
Crystal output. (for external reference clock leave unconnected)
3.3V volt I/O power supply.
Frequency select inputs. See function list table. Has pull up resistors
BUS clock outputs.
Spread Spectrum Enable. Low=enable.
High=Spread Spectrum down spread.
Low=Spread Spectrum center spread.
Core power supply. 3.3V
24MHz clock output
48MHz clock output.
No connect
Output Enable when this signal is Low all Bus Clocks, Fixed Clocks, CPU
Clocks outputs placed in tristate mode (internally pulled up)
CPU clocks outputs see functionality table for
specifications
frequency
Spread Spectrum Functionality
Input Pin 19
SS_EN#
0
1
Input Pin 20
SS_TYPE
0
1
X
CPU, SDRAM
and PCICLOCKS
Frequency modulated in
spread spectrum mode
+0.5%, -0.5% (nominally)
Frequency modulated in
spread spectrum mode
+0%, -2.0% (nominally)
Normal, Steady frequency
mode
REF, IOAPIC
14.318MHz
14.318MHz
14.318MHz
24MHz
24MHz
24MHz
24MHz
48MHz
48MHz
48MHz
48MHz
VDD Pins: 48, REFs, XTAL OSC
VDD Pins: 6, CPU 1- 2
VDD Pins: 15, BUS 1-6
VDD Pins: 24, 48, Fix PLL
VDD Pins: 28, CPU PLL CORE
VDD Pins: 32, CPU 3-6
VDD Pins: 40, CPU 7-10
VDD Pins: 46, CPU 11-12
2