ICS874004 Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – PCI EXPRESS JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 24
nQA0, QA0 Output
Differential output pair. LVDS interface levels.
2, 3
nQB0, QB0 Output
Differential output pair. LVDS interface levels.
4, 23
5
V_DDO
FB_OUT
Power
Output
Output supply pins.
Non-inverting differential feedback output.
6
nFB_OUT Output
Inverting differential feedback output.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
7
MR
Input
Pulldown
reset causing the true outputs (nQx) to go low and the inverted outputs
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
8
BW_SEL
Input
Pullup/
Pulldown
Selects PLL Band Width input. LVCMOS/LVTTL interface levels.
9
V_DDA
Power
Analog supply pin.
10
F_SEL
Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
11
V_DD
Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
12
OEA
Input
Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
13
CLK
Input Pulldown Non-inverting differential clock input.
14
nCLK
Input
Pullup Inverting differential clock input.
15
GND
Power
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
16
OEB
Input
Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
17
FB_IN
Input Pulldown Non-inverting differential feedback input.
18
nFB_IN
Input
Pullup Inverting differential feedback input.
19, 20 nQB1, QB1 Output
Differential output pair. LVDS interface levels.
21, 22
nQA1, QA1 Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs
OEA OEB
0
0
1
1
QAx/nQAx
HiZ
Enabled
Outputs
QBx/nQBx FB_OUT/nFB_OUT
HiZ
Enabled
Enabled
Enabled
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs
BW_SEL
0
1
Float
PLL
Bandwidth
~200KHz
~800KHz
~400KHz
874004AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 21, 2005
2