ICS85310I-21 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85310I-21
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V_CC
Power
2, 5
nc
Unused
Core supply pin.
No connect.
3
CLKA
Input Pulldown Non-inverting differential clock input.
4
nCLKA
Input
Pullup Inverting differential clock input.
6
CLKB
Input Pulldown Non-inverting differential clock input.
7
nCLKB
Input
Pullup Inverting differential clock input.
8
9, 16, 25, 32
10, 11
V_EE
V_CCO
nQB4, QB4
Power
Power
Output
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
12, 13
nQB3, QB3 Output
Differential output pair. LVPECL interface levels.
14, 15
nQB2, QB2 Output
Differential output pair. LVPECL interface levels.
17, 18
nQB1, QB1 Output
Differential output pair. LVPECL interface levels.
19, 20
nQB0, QB0 Output
Differential output pair. LVPECL interface levels.
21, 22
nQA4, QA4 Output
Differential output pair. LVPECL interface levels.
23, 24
nQA3, QA3 Output
Differential output pair. LVPECL interface levels.
26, 27
nQA2, QA2 Output
Differential output pair. LVPECL interface levels.
28, 29
nQA1, QA1 Output
Differential output pair. LVPECL interface levels.
30, 31
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
CLKA or CLKB nCLKA or nCLKB
Outputs
QA0:QA4,
QB0:QB4
nQA0:nQA4,
nQB0:nQB4
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential Non Inverting
1
0
HIGH
LOW
Differential to Differential Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
85310AYI-21
www.icst.com/products/hiperclocks.html
2
REV. D JUNE 30, 2005