ICS8520I-02 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11, 14, 24,
25, 35, 38, 48
V_DDO
Power
Output supply pins.
2, 3
Q11, nQ11 Output
Differential output pair. LVHSTL interface levels.
4, 5
Q10, nQ10 Output
Differential output pair. LVHSTL interface levels.
6, 19, 30, 43
GND
Power
Power supply ground.
7, 8
Q9, nQ9 Output
Differential output pair. LVHSTL interface levels.
9, 10
Q8, nQ8 Output
Differential output pair. LVHSTL interface levels.
12, 13
15, 16
V_DD
Q7, nQ7
Power
Output
Power supply pins.
Differential output pair. LVHSTL interface levels.
17, 18
Q6, nQ6 Output
Differential output pair. LVHSTL interface levels.
20, 21
Q5, nQ5 Output
Differential output pair. LVHSTL interface levels.
22, 23
Q4, nQ4 Output
Differential output pair. LVHSTL interface levels.
26, 27
Q3, nQ3 Output
Differential output pair. LVHSTL interface levels.
28, 29
Q2, nQ2 Output
Differential output pair. LVHSTL interface levels.
31, 32
Q1, nQ1 Output
Differential output pair. LVHSTL interface level
33, 34
Q0, nQ0 Output
Differential output pair. LVHSTL interface level
36
CLK
Input Pulldown Non inverting differential clock input.
37
nCLK
Input Pullup Inverting differential clock input.
39, 40
Q15, nQ15 Output
Differential output pair. LVHSTL interface levels.
41, 42
Q14, nQ14 Output
Differential output pair. LVHSTL interface levels.
44, 45
Q13, nQ13 Output
Differential output pair. LVHSTL interface levels.
46, 47
Q12, nQ12 Output
Differential output pair. LVHSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. FUNCTION TABLE
Inputs
CLK
nCLK
Outputs
Q0:Q15
nQ0:nQ15
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential Non Inverting
1
0
HIGH
LOW
Differential to Differential Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information Section, "Wiring the Differential input to accept single ended levels".
8520DYI-02
www.icst.com/products/hiperclocks.html
2
REV. B NOVEMBER 16, 2005