ICS844008I-15 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844008I-15
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2
Q0, nQ0 Output
Differential output pair. LVDS interface levels.
3, 12,
22, 27
V_DD
Power
Core supply pin.
4, 5
Q1, nQ1 Ouput
Differential output pair. LVDS interface levels.
6, 13,
19, 29
GND
Power
Power supply ground.
7, 8
Q2, nQ2 Output
Differential output pair. LVDS interface levels.
9
F_SEL
Input Pullup Frequency select pin LVCMOS/LVTTL interface levels.
10, 11 Q3, nQ3 Output
Differential output pair. LVDS interface levels.
14, 15 Q4, nQ4 Output
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
16
MR
Input
Pulld- causing the true outputs Qx to go low and the inverted outputs nQx
own to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
17, 18 nQ5, Q5 Output
Differential output pair. LVDS interface levels.
20, 21 nQ6, Q6 Output
Differential output pair. LVDS interface levels.
23, 24 nQ7, Q7 Output
Differential output pair. LVDS interface levels.
25
26
28
30, 31
32
V_DDA
nPLL_SEL
OE2
XTAL_OUT,
XTAL_IN
OE1
Power
Input
Input
Input
Input
Pulld-
own
Pullup
Pullup
Analog supply pin.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
Output enable for Q5/nQ5:Q7/nQ7 outputs.
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Output enable for Q0/nQ0:Q4/nQ4 outputs.
LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input PullUP Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3A. OE1 FUNCTION TABLE
Input Outputs
OE1 Q0:Q4, nQ0:nQ4
0 Places outputs in Hi-Z state
1 Normal operation
TABLE 3B. OE2 FUNCTION TABLE
Input Outputs
OE2 Q5:Q7, nQ5:nQ7
0 Places outputs in Hi-Z state
1 Normal operation
844008AYI-15
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 2, 2006