ICS844003I Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1
24
DIV_SELB0
DIV_SELB1
Input
Pulldown
Division select pin for Bank B. Default = Low.
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
2
VCO_SEL
Input
Pullup
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
3
MR
Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
4
V_{DDO_A}
Power
5, 6 QA0, nQA0 Ouput
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH,
7
CLK_ENB
Input
Pullup
the output pairs on Bank B are enabled. When logic LOW, the output pairs
are in a high impedance state. Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH,
8
CLK_ENA
Input
Pullup
the output pair in Bank A is enabled. When logic LOW, the output pair is in
a high impedance state. Has an internal pullup resistor so the default
power-up state of output is enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
9
FB_DIV
Input Pulldown for ÷20. When HIGH, the feedback divider is set for ÷24.
LVCMOS/LVTTL interface levels.
10
V
Power
DDA
Analog supply pin.
11
V_DD
Power
Core supply pin.
12
13
DIV_SELA0
DIV_SELA1
Input
Pullup
Division select pin for Bank A. Default = HIGH.
LVCMOS/LVTTL interface levels.
14
GND
Power
Power supply ground.
15, 16
17
18
XTAL_OUT,
XTAL_IN
TEST_CLK
XTAL_SEL
Input
Input
Input
Pulldown
Pullup
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected
by default. LVCMOS/LVTTL interface levels.
19, 20 nQB1, QB1 Output
Differential output pair. LVDS interface levels.
21, 22 nQB0, QB0 Output
Differential output pair. LVDS interface levels.
23
V
Power
DDO_B
Output supply pin for Bank B outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
844003AGI
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
www.icst.com/products/hiperclocks.html
REV. B AUGUST 25, 2005
2