ICS843003 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS843003
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
DIV_SELB0
Input
Pulldown
Division select pin for Bank B. Default = Low.
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
2
VCO_SEL Input
Pullup
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
3
MR
Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
4
V_{CCO_A}
Power
5, 6 QA0, nQA0 Ouput
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the
output pair on Bank B is enabled. When logic LOW, the output pair drives
7
OEB
Input Pullup differential Low (QB0=Low, nQB0=High). Has an internal pullup resistor so
the default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the
2 output pairs on Bank A are enabled. When logic LOW, the output pair
8
OEA
Input Pullup drives differential Low (QA0=Low, nQA0=High). Has an internal pullup
resistor so the default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
9
FB_DIV
Input Pulldown for ÷20. When HIGH, the feedback divider is set for ÷24.
LVCMOS/LVTTL interface levels.
10
V_CCA
Power
Analog supply pin.
11
V_CC
Power
Core supply pin.
12
DIV_SELA0 Input
Pullup
Division select pin for Bank A. Default = HIGH.
LVCMOS/LVTTL interface levels.
13
DIV_SELA1
Input
Pulldown
Division select pin for Bank A. Default = Low.
LVCMOS/LVTTL interface levels.
14
15, 16
17
18
V_EE
XTAL_OUT,
XTAL_IN
TEST_CLK
XTAL_SEL
Power
Input
Input
Input
Pulldown
Pullup
Negative supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected
by default. LVCMOS/LVTTL interface levels.
19, 20 nQB1, QB1 Output
Differential output pair. LVPECL interface levels.
21, 22 nQB0, QB0 Output
Differential output pair. LVPECL interface levels.
23
V_{CCO_B}
Power
Output supply pin for Bank B outputs.
24
DIV_SELB1 Input
Pullup
Division select pin for Bank B. Default = High.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
843003AG
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2
REV. A JULY 27, 2004