ICS426 Datasheet, PDF (2/6 Pages) Integrated Circuit Systems – Serial ATA/Fibre Channel Clock Synthesizer

ICS426
Serial ATA/Fibre Channel Clock Synthesizer
Pin Assignment
X1/ICLK
1
VDD
2
VDD
3
GND
4
GND
5
S1
6
VDD
7
CLK
8
16
X2
15
GND
14
GND
13
OE
12
GND
11
S0
10
VDD
9
GND
16 pin 173 mil (0.65 mm) TSSOP
Clock Output Select Table (MHz)
S1 S0
0
0
0
1
1
0
1
1
Input
25
25
25
25
CLK Output
75
150
106.25
156.25
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
X1/ICLK
VDD
VDD
GND
GND
S1
VDD
CLK
GND
VDD
S0
GND
OE
GND
GND
X2
Pin
Type
Pin Description
XI Crystal connection. Connect to a 25 MHz fundamental mode
crystal or clock input.
Power Connect to +3.3 V.
Power Connect to +3.3 V.
Power Connect to ground.
Power Connect to ground.
Input Select pin 1 determines CLK output based on table above. Internal
pull-up.
Power Connect to +3.3 V.
Output Clock output. Tri-state output when OE is low.
Power Connect to ground.
Power Connect to +3.3V.
Input Select pin 0 determines CLK output based on table above. Internal
pull-up.
Power Connect to ground.
Input Output Enable. All outputs are tri-stated when low. Internal pull-up.
Power Connect to ground.
Power Connect to ground.
XO Crystal connection. Connect to a 25 MHz fundamental mode
crystal or float for clock input.
MDS 426 B
2
Revision 091102
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