ICS421-05 Datasheet, PDF (2/5 Pages) Integrated Circuit Systems – DIGITAL VIDEO CAMERA CLOCK

ICS421-05
DIGITAL VIDEO CAMERA CLOCK
Pin Assignment
CLKIN 1
VDD 2
GND 3
24.576M 4
8 OE_USB
7 12M
6 VDD
5 72M
8 pin (173 mil) TSSOP
OE_USB Operation Table
OE_USB
0
1
Function
Output tri-state
Output running
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
VDD
GND
24.576M
72M
VDD
12M
OE_USB
Pin
Type
Input
Power
Power
Output
Output
Power
Output
Input
Pin Description
27 MHz single ended clock input.
Connect to voltage supply.
Connect to ground.
24.576 MHz clock output.
72 MHz clock output for CCD.
Connect to voltage supply.
12 MHz clock output for USB.
Output enable for 12M clock for USB. See table for functionality,
internal pull-down.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS421-05 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS421-05. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
MDS 421-05 B
2
Revision 072304
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