ICS2510C Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – 3.3V Phase-Lock Loop Clock Driver

ICS2510C
Pin Descriptions
PIN NUMBER PIN NAME
1
AGND
2, 10, 14 VCC
3
CLK0
4
CLK1
5
CLK2
6, 7, 18, 19 GND
8
CLK3
9
CLK4
11
OE¹
12
FBOUT
13
FBIN
15
CLK5
16
CLK6
17
CLK7
20
CLK8
21
CLK9
22
VCC
23
AVCC
24
CLKIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
PWR
IN
IN
Analog Ground
Power Supply (3.3V)
Buffered clock output.
Buffered clock output.
Buffered clock output.
Ground
Buffered clock output.
Buffered clock output.
DESCRIPTION
Output enable (has internal pull_up). When high, normal operation.
When low, clock outputs are disabled to a logic low state.
Feedback output
Feedback input
Buffered clock output.
Buffered clock output.
Buffered clock output.
Buffered clock output.
Buffered clock output.
Power Supply (3.3V) digital supply.
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
Clock input
Note:
1. Weak pull-ups on these inputs
Functionality
INPUTS
OUTPUTS
OE
AVCC CLK (9:0) FBOUT
0
3.33
0
Driven
1
3.33
Driven
Driven
Buffer Mode
0
0
0
Driven
1
0
Driven
Driven
Test mode:
When AVCC is 0, shuts off the PLL
and connects the input directly to the output buffers
Source
PLL
PLL
CLKIN
CLKIN
PLL
Shutdown
N
N
Y
Y
2