AV9110 Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – Serially Programmable Frequency Generator

AV9110
Pin Configuration
14 Pin Dip, SOIC
Clock Reference Implementations:
AV9110-01 vs. AV9110-02
The AV9110 requires a stable reference clock (5 to 32 MHz) to
generate a stable, low jitter output clock. The AV9 11 0 -01 is
optimized to use an external quartz crystal as a frequency
reference, without the need of additional external components.
The AV9110-02 is optimized to accept an TTL clock
reference. Either device can be used with an external crystal
or accept a TTL clock reference, although extra components
may be required. The various combinations implied are
summarized in Figure 2 (see page 7).
Pin Descriptions
PIN NUMBER
PIN NAME
1
X1
2
AVDD
3
AGND
4
VDD
5
GND
6
DATA
7
SCLK
8
CE#
9
CLK/X
10
GND
11
VDD
12
CLK
13
OE
14
X2
PIN
TYPE
Input
Power
Power
Power
Power
Input
Input
Input
Output
Power
Power
Output
Input
Output
DESCRIPTION
Crystal input or TTL reference clock.
ANALOG power supply. Connect to +5V.
ANALOG GROUND.
Digital power supply. Connect to +5V.
Digital GROUND.
Serial DATA pin.
SERIAL CLOCK. Clocks shift register.
CHIP ENABLE. Active low, controls data transfer.
CMOS CLOCK divided by X output.
Digital GROUND.
Digital power supply. Connect to +5V.
CMOS CLOCK output.
OUTPUT ENABLE. Tristates both outputs when low.
Crystal input or TTL reference clock.
2