ICS9LPR501 Datasheet, PDF (19/22 Pages) Integrated Circuit Systems – 64-pin CK505 w/Fully Integrated Voltage Regulator

Integrated
Circuit
Systems, Inc.
Byte 22 CPU M/N Programming
Bit Pin
Name
7
N Div bit 8
6
N Div bit 9
5
M Div Bit 5
4
M Div Bit 4
3
M Div Bit 3
2
M Div Bit 2
1
M Div Bit 1
0
M Div Bit 0
Description
PLL 1 M/N Programming
(Intel PLL1 CPU)
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 23 CPU M/N Programming
Bit Pin
Name
7
N Div bit 7
6
N Div bit 6
5
N Div bit 5
4
N Div bit 4
3
N Div bit 3
2
N Div bit 2
1
N Div bit 1
0
N Div Bit 0
Description
PLL 1 M/N Programming
(Intel PLL1 CPU)
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 24 CPU Divider Programming
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
CPUDiv3
2
CPUDiv2
1
CPUDiv1
0
CPUDiv0
Description
Reserved
CPU Divider Ratio Programming Bits
Byte 25 SRC and PCI Divider Programming (CK505 PLL1)
Bit Pin
Name
Description
7
PCIDiv3
6
PCIDiv2
PCI Divider Ratio Programming Bits for PLL1
5
PCIDiv1
4
PCIDiv0
3
SRCDiv3
2
SRCDiv2
SRC Divider Ratio Programming Bits
1
SRCDiv1
0
SRCDiv0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 63 Special Power Management Features (Rev P Silicon and Higher)
Bit Pin
Name
Description
RW
7
Internal flags
RW
6
RW
5
RW
4
RW
3
RW
2
RW
1
SATA PLL
Power Management Feature
RW
0
XTAL PD Control
Controls XTAL on/off in legacy PD
RW
0
0
0
0000:/2
0001:/3
0010:/5
0011:/7
0
0000:/2
0001:/3
0010:/5
0011:/9
0000:/2
0001:/3
0010:/5
0011:/9
0
off
off
ICS9LPR501
1
1
1
1000:/8
1001:/12
1010:/20
1011:/28
1
1000:/8
1001:/12
1010:/20
1011:/36
1000:/8
1001:/12
1010:/20
1011:/36
1
on
on
Default
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
Default
0
0
0
0
X
X
X
X
Default
X
X
X
X
X
X
X
X
Default
0
0
0
0
0
0
0
1
1118E—08/08/07
19