ICS853111-02 Datasheet, PDF (12/18 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS853111-02 LVPECL buffer. Figure 6 shows a schematic ex-
ample of the ICS853111-02 LVPECL clock buffer. In this ex-
ample, the input is driven by an LVPECL driver. CLK_SEL is set
at logic high to select PCLK0/nPCLK0 input.
Zo = 50
+
Zo = 50
-
VCC
R2
R1
50
50
VCC
C6 (Option)
R3
0.1u
50
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
R9
50
C8 (Option)
0.1u
R4
1K
R10
50
R11
50
1
2
3
4
VCC
CLK_SEL
PCLK0
5
6
7
8
nPCLK0
VBB
PCLK1
nPCLK1
VEE
VCC
VCC=3.3V
(U1-9)
(U1-16)
VCC
(U1-25) (U1-32) (U1-1)
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0. 1uF
C5
0. 1uF
Q3
nQ3
Q4
24
23
22
21
nQ4
Q5
nQ5
Q6
20
19
18
17
nQ6
U1
I C S853111
Zo = 50
Zo = 50
+
-
R8
R7
50
50
C7 (Option)
0.1u
R13
50
FIGURE 6. EXAMPLE ICS853111-02 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
solder as shown in Figure 7. For further information, please re-
fer to the Application Note on Surface Mount Assembly of
Amkor’s Thermally /Electrically Enhance Leadframe Base Pack-
age, Amkor Technology.
SOLDER M ASK
EXPOSED PAD
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
853111AY-02
GROUND PLANE
THERMAL VIA
Expose Metal Pad
(GROUND PAD)
FIGURE 7. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
www.icst.com/products/hiperclocks.html
12
REV. A JANUARY 10, 2006