ICS84320-01K Datasheet, PDF (10/16 Pages) Integrated Circuit Systems – 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84320-01K
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS84320-01K layout example used in
this layout guideline is shown in Figure 5A. The ICS84320-01K
recommended PCB board layout for this example is shown in
Figure 5B. This layout example is used as a general guideline.
The layout in the actual system will depend on the selected com-
ponent types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
84320AK-01
U1
1
2
3
4
5
M5
M6
M7
M8
6
7
8
N0
N1
nc
VEE
ICS84320-01
C14
0.1u
C1
C2
X1
VCC
XTAL2
T_CLK
24
23
22
REF _I N
XTAL_SEL
nXTAL_SEL ₂₁
VCCA _{20 S_LOAD}
S_LOAD
S_DATA
19
18
S_DATA
S_CLOCK
S_CLOCK ₁₇
MR
VCCA
C11
0.01u
R7
24
C16
10u
C15
0.1u
Zo = 50 Ohm
IN+
TL1
Zo = 50 Ohm
IN-
TL2
VCC
R1
R3
125
125
+
-
R2
R4
84
84
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT
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10
REV. A FEBRUARY 6, 2004