ICS843002 Datasheet, PDF (10/16 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure 4A shows a schematic example of the ICS843002. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
parallel resonant 26.5625MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy.
VCC
R2
10 C3
10uF
Logic Control Input Examples
VCCA
C4
0. 01u
VCC
C6
0. 1u
Set Logic
VCC
Input to
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VCC
Input to
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
C2
33pF
X1
18pF
26.5625 MHz
C1
27pF
Zo = 50 Ohm
VCCO
C7
0.1u
U1
ICS843002
Zo = 50 Ohm
R4
50
VCC=3.3V
VCCO=3.3V
Zo = 50 Ohm
VCCO
C8
0.1u
Zo = 50 Ohm
R7
50
+
-
R6
50
R5
50
+
-
R8
50
R9
50
C9
0. 1u
FIGURE 4A. ICS843002 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of ICS843002 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5, C6, C7, C8
0603
R2
0603
NOTE: Table 6, lists component sizes
shown in this layout example.
FIGURE 4B. ICS843002 PC BOARD LAYOUT EXAMPLE
843002AG
www.icst.com/products/hiperclocks.html
10
REV. B MAY 6, 2005