8T49N242 Datasheet, PDF (10/65 Pages) Integrated Circuit Systems – Open-drain Interrupt pin

8T49N242 DATA SHEET
Output Enable Operation
When GPIO[1:0] are used as Output Enable control signals, the
function of the pins is to select one of four register-based maps that
indicate which outputs should be enabled or disabled.
00
Q0 Q1 Q2 Q3
EN EN EN EN
0 1 DIS EN EN DIS
4
1 0 EN DIS EN DIS
1 1 DIS DIS DIS DIS
Figure 4. Output Enable Map Operation
Device Hardware Configuration
The 8T49N242 supports an internal One-Time Programmable (OTP)
memory that can be pre-programmed at the factory with one
complete device configuration. Some or all of this pre-programmed
configuration will be loaded into the device’s registers on power-up or
reset.
These default register settings can be over-written using the serial
programming interface once reset is complete. Any configuration
written via the serial programming interface needs to be re-written
after any power cycle or reset. Please contact IDT if a specific
factory-programmed configuration is desired.
Device Start-up & Reset Behavior
The 8T49N242 has an internal power-up reset (POR) circuit and a
Master Reset input pin nRST. If either is asserted, the device will be
in the Reset State.
For highly programmable devices, it’s common practice to reset the
device immediately after the initial power-on sequence. IDT
recommends connecting the nRST input pin to a programmable logic
source for optimal functionality. It is recommended that a minimum
pulse width of 10ns be used to drive the nRST input.
While in the reset state (nRST input asserted or POR active), the
device will operate as follows:
• All registers will return to & be held in their default states as
indicated in the applicable register description.
• All internal state machines will be in their reset conditions.
• The serial interface will not respond to read or write cycles.
• The GPIO signals will be configured as Output Enable inputs.
• All clock outputs will be disabled.
• All interrupt status and Interrupt Enable bits will be cleared,
negating the nINT signal.
Upon the later of the internal POR circuit expiring or the nRST input
negating, the device will exit reset and begin self-configuration.
The device will load an initial block of its internal registers using the
configuration stored in the internal One-Time Programmable (OTP)
memory. Once this step is complete, the 8T49N242 will check the
register settings to see if it should load the remainder of its
configuration from an external I²C EEPROM at a defined address or
continue loading from OTP, or both. See Section, “I2C Boot-up
Initialization Mode” for details on how this is performed.
Once the full configuration has been loaded, the device will respond
to accesses on the serial port and will attempt to lock the PLL to the
crystal and begin operation. Once the PLL is locked, all the outputs
derived from it will be synchronized and output phase adjustments
can then be applied if desired.
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave
in an I²C compatible configuration, to allow access to any of the
internal registers for device programming or examination of internal
status. All registers are configured to have default values. See the
specifics for each register for details.
The device has the additional capability of becoming a master on the
I²C bus only for the purpose of reading its initial register
configurations from a serial EEPROM on the I²C bus. Writing of the
configuration to the serial EEPROM must be performed by another
device on the same I²C bus or pre-programmed into the device prior
to assembly.
FEMTOCLOCK^®NG UNIVERSAL FREQUENCY TRANSLATOR
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REVISION 2 08/07/15