MK2308-2 Datasheet, PDF (1/5 Pages) Integrated Circuit Systems – ZERO DELAY LOW SKEW BUFFER

MK2308-2
ZERO DELAY, LOW SKEW BUFFER
Description
The MK2308-2 is a low jitter, low skew, high
performance Phase-Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides eight low skew outputs at speeds up to 160
MHz at 3.3 V. The MK2308-2 includes a bank of four
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all eight outputs. Compared to competitive
CMOS devices, the MK2308-2 has the lowest jitter.
Features
• Packaged in 16-pin SOIC
• Zero input-output delay
• Four 1X outputs plus four 1/2X outputs
• Output to output skew is less than 250 ps
• Output clocks up to 160 MHz at 3.3 V
• Ability to generate 2X the input
• Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V
• Spread Smart^TM technology works with spread
spectrum clock generators
• Advanced, low power, sub micron CMOS process
• Operating voltage of 3.3 V or 5 V
Block Diagram
FBIN
CLKIN
VDD
2
PLL
/2
S2, S1 ²
Control
Logic
2
GND
CLKA1
CLKA2
CLKA3
BANK
A
CLKA4
CLKB1
CLKB2
CLKB3
BANK
B
CLKB4
MDS 2308-2 B
1
Revision 111103
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com