MK2308-1 Datasheet, PDF (1/6 Pages) Integrated Circuit Systems – 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

MK2308-1
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Description
The MK2308-1 is a low phase noise, high-speed PLL
based, 8-output, low-skew zero delay buffer. Based on
ICS’ proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides eight low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly
from the input (for testing), and can be set to tri-state
mode or to stop at a low level. For normal operation as
a zero delay buffer, any output clock is tied to the FBIN
pin.
ICS manufactures a variety of clock generators and
buffers.
Features
• Clock outputs from 10 to 133 MHz
• Zero input-output delay
• Eight low skew (<200 ps) outputs
• Device-to-device skew <700 ps
• Full CMOS outputs with 25 mA output drive
capability at TTL levels
• 5 V tolerant FBIN and CLKIN pins
• Tri-state mode for board-level testing
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V
• Industrial temperature range available
• Packaged in 16-pin SOIC
Block Diagram
S2, S1 ²
CLKIN
FBIN
Control
Logic
VDD
2
Clock
1
Synthesis
PLL
0
GND ²
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Feedback is shown from CLKB4 for
illustration, but may come from any output.
MDS 2308-1 A
1
Revision 100603
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com