MK2069-04 Datasheet, PDF (1/19 Pages) Integrated Circuit Systems – VCXO-Based Universal Clock Translator

MK2069-04
VCXO-Based Universal Clock Translator
Description
The MK2069-04 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that features a PLL
(Phase-Locked Loop) input reference divider and
feedback divider that have a wide numeric range
selectable by the user. This enables a complex PLL
multiplication ratio that can be used for translation
between clock frequency standards.
The on-chip VCXO produces a stable, low jitter output
clock using a phase detector frequency down to 8 kHz
or lower. This means the MK2069-04 can translate
between clock frequencies that have a low common
denominator, such as the 8 kHz frame clock common
with telecom standards. The MK2069-04 also provides
jitter attenuation of the input clock and can accept a low
input frequency as well.
The device is optimized for user configurability by
providing access to all major PLL divider functions. No
power-up programming is needed as configuration is
pin selected. External VCXO loop filter components
provide an additional level of user configurability.
The MK2069-04 includes a lock detector (LD) output
that serves as a clock status monitor. The clear (CLR)
input enables rapid synchronization to the phase of a
newly selected input clock.
Block Diagram
Features
• Input clock frequency <1kHz to 170MHz
• Output clock frequency of 500kHz to 160MHz
• Clock translation examples:
T1 (1.544MHz) to/from E1 (2.048MHz)
T3 (44.736MHz) to/from E3 (34.368MHz)
OC-3 (155.52MHz) to/from T1 (1.544 MHz)
CCIR-601 (27MHz) to/from SMPTE 274M
(74.125MHz)
• Jitter attenuation of input clock provided by VCXO
circuit. Jitter transfer characteristics user configured
through external loop filter component selection.
• Low jitter and phase noise generation.
• PLL lock status output
• PLL Clear function allows seamless synchronizing to
an altered input clock phase
• 2nd PLL provides frequency translation of VCXO
PLL output (VCLK) to a higher or alternate output
frequency (TCLK).
• Device will free-run in the absence of an input clock
based on VCXO frequency.
• 56 pin TSSOP package
• Single 3.3V power supply
• 5V tolerant clock input
IC L K
CLR
RPV
RV11:0
12
ISET LF
P u lla b le
xtal
LFR X1
X2
SV1:0
2
RPV
D iv id e r
1, 8
RV
D iv id e r
2 to 4097
Phase
D e te c to r
VCXO
PLL
VCXO
Charge
Pump
FV Divider
1 to 4096
SV
D iv id e r
1,2,12,16
Lock Detector
12
FV11:0
LDC
ST
VCO
ST
D ivid e r
2, 16
T ra n s la to r
PLL
FT Divider
2 to 16, even only
LDR
3
FT2:0
VDD
4
VCLK
OEV
TCLK
OET
4
GND
RCLK
OER
LD
OEL
MDS 2069-04 F
1
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel [phone] l www.icst.com