MK2069-01 Datasheet, PDF (1/19 Pages) Integrated Circuit Systems – VCXO-Based Line Card Clock Synchronizer

MK2069-01
VCXO-Based Line Card Clock Synchronizer
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable,
jittery input clock and provide a de-jittered, low phase
noise output clock at a user determined frequency. The
device’s clock multiplication ratios are user selectable
since all major PLL divider blocks can be configured
through device pin settings. External PLL loop filter
components allow tailoring of the VCXO PLL loop
response and therefore the clock jitter attenuation
characteristics.
The MK2069-01 is ideal for line card applications. Its
three input MUX enables selection of the master or
slave (backup) system clocks, as well as a backup local
line card clock. The lock detector (LD) output serves as
a clock status monitor. The clear (CLR) input enables
rapid synchronization to the phase of a newly selected
input clock, while eliminating the generation of extra
clock cycles and wander caused by memory in the PLL
feedback divider. CLR also serves as a temporary
holdover function when kept low.
Features
• Input clock frequency of 1kHz to 170MHz
• Output clock frequency of 500kHz to 160MHz
• Jitter attenuation of input clock provided by VCXO
circuit. Jitter transfer characteristics user configured
through selection of external loop filter components.
• 3:1 Input MUX for input reference clocks
• PLL lock status output
• PLL Clear function allows seamless synchronizing to
an altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
• VCXO-based clock generation offers very low jitter
and phase noise generation, even with a low
frequency or jittery input clock.
• 2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies
(TCLK).
• Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
• 56 pin TSSOP package
• Single 3.3V power supply
• 5V tolerant inputs on ICLK0 and ICLK1
Block Diagram
R V 1 :0
2
IS E T
P u lla b le
xtal
SV2:0
LF
LFR X1
X2
3
R T 1 :0
2
ST1:0
2
IC L K 0
IC L K 1
IC L K 2
0X
RV
10
D iv id e r
1,2,4,128
01
Phase
Detector
2
M X 1:0
VCXO
PLL
CLR
VCXO
Charge
Pump
FV Divider
1-4096
SV
D iv id e r
1,2,4,6,8,
10,12,16
RT
D iv id e r
1-4
VCO
ST
D iv id e r
2,4,8,16
Translator
PLL
FT Divider
1-64
Lock Detector
12
FV11:0
LDC
LDR
6
FT5:0
VDD
4
VCLK
OEV
TCLK
OET
4
GND
RCLK
OER
LD
OEL
MDS 2069-01 H
1
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel [phone] l www.icst.com