MK2049-01 Datasheet, PDF (1/11 Pages) Integrated Circuit Systems – Communications Clock PLL

MK2049-01
Communications Clock PLL
Description
The MK2049 is a Phase-Locked Loop (PLL) based
clock synthesizer, which accepts an 8 kHz clock
input as a reference and generates T1, E1, T3, E3,
and OC3 frequencies. The device can also accept a
T1, E1, T3, or E3 input clock and provide the
same output for loop timing. All outputs are
frequency locked together and to the input. This
allows for the generation of locked clocks to an
8 kHz backplane clock, simplifying clock
distribution in communications systems.
MicroClock can customize this device for many
other different frequencies. Contact your
MicroClock representative for more details.
For a fixed input-output phase relationship, refer
to the MK2049-02, -03, or -3x. The MK2049-3x
are 3.3 V devices.
Block Diagram
VDD GND
44
Features
• Packaged in 20 pin SOIC
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock or
Loop Timing frequencies
• Locks to 8 kHz ±100 ppm (External mode)
• Exact internal ratios eliminate the need for external
dividers
• Zero ppm synthesis error in all output clocks.
• Output clock rates include T1, E1, T3, E3, and
OC3÷8
• 5 V ±5% operation
• Offered in Commercial and Industrial temperature
versions
FS3:0 ⁴
Clock
Input
Reference
Crystal
X1
Crystal
Oscillator
X2
External/
Loop
Timing
Mux
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
8 kHz
CAP1
CAP2
MDS 2049-01 J
1
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone]tel •www.icst.com