M906-01 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – VCSO BASED GBE CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
Product Data Sheet
M906-01
VCSO BASED GBE CLOCK GENERATOR
GENERAL DESCRIPTION
The M906-01 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. It is ideal for
Gigabit Ethernet. The output clock
(frequency of 156.25 or 187.50MHz
for example) is provided from six
LVPECL clock output pairs. (Specify frequency at time
of order.) The accuracy of the output frequency is
assured by the internal PLL, which phase-locks the
internal VCSO to the reference input frequency (25 or
30MHz for example). The input reference can either
be an external crystal, utilizing the internal crystal
oscillator, or a stable external clock source such as
a packaged crystal oscillator.
FEATURES
◆ Output clock frequency from 125MHz to 190MHz
(Consult factory for frequency availability)
◆ Six identical LVPECL output pairs
◆ Integrated SAW (surface acoustic wave) delay line
◆ Low jitter 0.7ps RMS (over 12kHz-20MHz)
◆ Ideal for Gigabit Ethernet clock reference
◆ Output-to-output skew < 100ps
◆ External XTAL or LVCMOS reference input
◆ Selectable external feed-through clock input
◆ STOP clock control (Logic 1 stops output clocks)
◆ Industrial temperature grade available
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
◆ Pb-free design/construction on all 9 x 9 mm modules
SIMPLIFIED BLOCK DIAGRAM
M906-01-156.25
PIN ASSIGNMENT (9 x 9 mm SMT)
XTAL_2
FOUT4
nFOUT4
FOUT5
nFOUT5
VCC
DNC
DNC
DNC
28
18
29
17
30
16
31 _{M 9 0 6 - 0 1} 15
32
14
33
(Top View)
13
34
12
35
11
36
10
nFOUT2
FOUT2
nFOUT1
FOUT1
GND
nFOUT0
FOUT0
VCC
GND
Figure 1: Pin Assignment
Example Output Frequency Configurations
Ref Clock
Frequency
(MHz)
PLL
Ratio
Output
Frequency ¹
(MHz)
Application
20
125
GbE
25
25/4
156.25
10GbE
30
187.50
12GbE
Table 1: Example Output Frequency Configurations
Note 1:Specify output clock frequency at time of order
VSCO
External
Crystal
Frequency
or
XTAL
OSC
Divider
Multiplying
O
Reference
PLL
1
Clock Input
(e.g., 25 or 30MHz)
LVPECL
Output
Clock Pairs
(e.g., 156.25
or 187.50MHz)
External
External
Loop Filter
Clock
Input
Figure 2: Simplified Block Diagram
External Output
Clock Clock STOP
Select Control
M906-01 Datasheet Rev 3.2
Revised 15Jun2006
M906-01 VCSO Based GbE Clock Generator
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel [phone]