M2080-2087 Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN

Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n _M2080/81/82
M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2080/81/82 and M2085/86/87 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
◆ Integrated SAW delay line; Output of 15 to 700 MHz ^*
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ LVPECL clock output (CML and LVDS options available)
◆ Pin-selectable PLL divider ratios support FEC ratios
• M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping
• M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping
• M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
◆ AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆ Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆ Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28
18
29
17
30
M2080
16
31
15
32
Series
14
33
13
34
(Top View)
12
35
11
36
10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2081-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
Base Input Rate ¹
(MHz)
Output Clock
(either output)
MHz
1/1
237/255
238/255
622.0800
666.5143
669.3266
622.08
or
155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
M2080 Series
MUX
0
Rfec
Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL Phase
Detector
Mfec Div
2
FEC_SEL1:0
2
FIN_SEL1:0
3
P_SEL2:0
Mfec / Rfec Divider
LUT
Mfin Divider
LUT
Loop Filter
Mfin Divider
(1, 4, 8, 32 or
1, 4, 8, 16)
VCSO
P Divider
(1, 4, 8, 32 or TriState)
Tri-state
P Divider
LUT
Figure 2: Simplified Block Diagram
LOL
FOUT
nFOUT
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
Revised 30Jul2004
M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel [phone]