M2050 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – SAW PLL FOR 10GBE 64B/66B FEC

Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n _M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2050/51/52 is a VCSO (Voltage Controlled SAW
Oscillator) based clock PLL
designed for FEC clock ratio
translation in 10Gb optical systems
such as 10GbE 64b/66b. It supports
both mapping and de-mapping of
64b/66b encoding and FEC
(Forward Error Correction) clock
multiplication ratios. The ratios are pin-selected from
pre-programming look-up tables.
FEATURES
◆ Integrated SAW delay line; Output of 15 to 700 MHz ^*
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50Hz to 80MHz)
◆ Pin-selectable PLL divider ratios support 64b/66b and
FEC encoding/decoding ratios:
• M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC
• M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE
• M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN
◆ Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Loss of Lock (LOL) output pin
◆ Narrow Bandwidth control input (NBW Pin)
◆ Hitless Switching (HS) options with or without Phase
Build-out (PBO) available; performance conforms with
SONET (GR-253) /SDH (G.813) MTIE and TDEV during
reference clock reselection
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28
18
29
17
30
M2050
16
31
M2051
15
32
M2052
14
33
13
34
(Top View)
12
35
11
36
10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2050 Mapper PLL
Base Input
Rate (MHz)¹
Mapper Ratio
Mfec / Rfec
(Pin Selectable)
VCSO* and Base
Output Rate
(MHz)²
625.0000
33 / 32
644.5313
625.0000
15 / 14
669.6429
644.5313
15 / 14
690.5692
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be base rate divided by “Mfin”.
Note 2: Output rate can be base rate divided by “P”.
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
M2050, 51, 52
Loop
Filter
NBW
LOL
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
MUX
0 _Rfec
Div
1
Phase
Detector
VCSO
REF_SEL
2
FEC_SEL1:0
FIN_SEL1:0 ²
3
P_SEL2:0
Mfec and Rfec
Divider
LUT
Mfec Div
Mfin Divider
(1, 4, 5, 25)
Mfin Divider
LUT
P Divider _TriState
(1, 4, 5, 25 or TriState)
P Divider
LUT
Figure 2: Simplified Block Diagram
FOUT0
nFOUT0
FOUT1
nFOUT1
M2050/51/52 Datasheet Rev 1.0
Revised 23Jun2005
M2050/51/52 SAW PLL for 10GbE 64b/66b FEC
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel [phone]