M2006-12A Datasheet, PDF (1/10 Pages) Integrated Circuit Systems – VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING

Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING
GENERAL DESCRIPTION
The M2006-12A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
Clock multiplication ratios (including
forward and inverse FEC) are
pin-selected from pre-programming
look-up tables. Includes Hitless
Switching and Phase Build-out to
enable SONET (GR-253) / SDH (G.813) MTIE and
TDEV compliance during reference clock reselection.
Hitless Switching (HS) engages when a 4ns or greater
clock phase change is detected.
This phase-change triggered implementation of HS is
not recommended when using an unstable reference
(more than 1ns jitter pk-to-pk) or when the resulting
phase detector frequency is less than 5MHz.
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
28
18
29
17
30
16
31 _{M 2 0 0 6 - 1 2 A} 15
32
14
33
(Top View)
13
34
12
35
11
36
10
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
FEATURES
◆ Reduced intrinsic output jitter and improved power
supply noise rejection compared to M2006-12
◆ Similar to the M2006-02A - and pin-compatible - but
adds Hitless Switching and Phase Build-out functions
◆ Includes APC pin for Phase Build-out function (for
absorption of the input phase change)
◆ Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation
◆ Input reference and VCSO frequencies up to 700MHz
(Specify VCSO frequency at time of order)
◆ Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Commercial and Industrial temperature grades
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Combinations
Using M2006-12A-622.0800
PLL Ratio Input Clock (MHz) Output Clock (MHz)
1/1
237/255
(inverse FEC)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
622.08
or
155.52
Table 1: Example I/O Clock Combinations Using M2006-12A-622.0800
Using M2006-12A-669.3266
PLL Ratio Input Clock (MHz) Output Clock (MHz)
237/255
(FEC rate)
1/1
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
669.3266
or
167.3316
Table 2: Example I/O Clock Combinations Using M2006-12A-669.3266
SIMPLIFIED BLOCK DIAGRAM
M2006-12A
Loop
Filter
APC
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
0
Rfec Div
1
VCSO
Mfec Div
Mfin Div
(1, 4, 8, or 32)
P0 Div
(1 or 4)
FOUT0
nFOUT0
4
FEC_SEL3:0
2
FIN_SEL1:0
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
P1 Div
(1 or 4)
FOUT1
nFOUT1
P0_SEL
Figure 2: Simplified Block Diagram
P1_SEL
M2006-12A Datasheet Rev 1.0
Revised 28Jul2004
M2006-12A VCSO Based FEC Clock PLL with Hitless Switching
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel [phone]