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ICS9LPR426A Datasheet, PDF (1/21 Pages) Integrated Circuit Systems – Low Power Programmable Timing Control Hub™ for P4™ processor
Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
Low Power Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
Key Specifications:
Low Power CK410M Compliant Main Clock
• CPU outputs cycle-cycle jitter < 85ps
• PCIEX outputs cycle-cycle jitter < 125ps
Output Features:
• SATA outputs cycle-cycle jitter < 125ps
• 2 - 0.7V push-pull differential CPU pairs
• PCI outputs cycle-cycle jitter < 500ps
• 5 - 0.7V push-pull differential PCIEX pairs
• 1 - 0.7V push-pull differential SATA pair
• +/- 100ppm frequency accuracy on CPU, PCIEX and
SATA clocks
• 1 - 0.7V push-pull differential CPU/PCIEX selectable pair • +/- 100ppm frequency accuracy on USB clocks
• 1 - 0.7V push-pull differential 27MHz/LCDCLK/PCIEX
selectable pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 2 - REF, 14.318MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCIEX
• Supports programmable spread percentage and
frequency
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• PEREQ# pins to support PCIEX power management.
• Low power differential clock outputs (No 50W resistor
to GND needed)
Pin Configuration
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
*SELPCIEX0_LCD#PCICLK5 5
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
*SELLCD_27#/PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
FSLA/USB_48MHz 12
GND 13
DOTT_96MHzL 14
DOTC_96MHzL 15
FSLB/TEST_MODE 16
27FIX/LCD_SSCGT/PCIeT_L0 17
27SS/LCD_SSCGC/PCIeC_L0 18
PCIeT_L1 19
PCIeC_L1 20
VDDPCIEX 21
PCIeT_L2 22
PCIeC_L2 23
PCIeT_L3 24
PCIeC_L3 25
SATACLKT_L 26
SATACLKC_L 27
VDDPCIEX 28
56 PCICLK2/REQ_SEL**
55 PCI&PCIEX_STOP#
54 CPU_STOP#
53 REF1/FSLC/TEST_SEL
52 REF0
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
45 GND
44 CPUT_L0
43 CPUC_L0
42 VDDCPU
41 CPUT_L1
40 CPUC_L1
39 VDD
38 GNDA
37 VDDA
36 CPUITPT_L2/PCIeT_L6
35 CPUITPC_L2/PCIeC_L6
34 VDDPCIEX
33 PEREQ1#/PCIeT_L5
32 PEREQ2#/PCIeC_L5
31 PCIeT_L4
30 PCIeC_L4
29 GND
56-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
1346–10/23/07
Functionality Table
Bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 2 Bit 1 Bit 0
Bit 3
FSLC FSLB FSLA
CPU
MHz
PCIEX
MHz
0
0
0
0 266.66 99.75
0
0
0
1 133.33 99.75
0
0
1
0 200.00 99.75
0
0
1
1 166.66 99.75
0
1
0
0 333.33 99.75
0
1
0
1 100.00 99.75
0
1
1
0 400.00 99.75
0
1
1
1 200.00 99.75
1
0
0
0 266.66 99.75
1
0
0
1 133.33 99.75
1
0
1
0 200.00 99.75
1
0
1
1 166.66 99.75
1
1
0
0 333.33 99.75
1
1
0
1 100.00 99.75
1
1
1
0 400.00 99.75
1
1
1
1 200.00 99.75
0
0
0
0 269.33 100.75
0
0
0
1 271.99 101.75
0
0
1
0 274.66 102.74
0
0
1
1 277.33 103.74
0
1
0
0 279.99 104.74
0
1
0
1 282.66 105.74
0
1
1
0 285.33 106.73
0
1
1
1 287.99 107.73
1
0
0
0 269.33 108.73
1
0
0
1 271.99 109.73
1
0
1
0 274.66 110.72
1
0
1
1 277.33 111.72
1
1
0
0 279.99 112.72
1
1
0
1 282.66 113.72
1
1
1
0 285.33 114.71
1
1
1
1 287.99 115.71
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
SATA
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
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