ICS97ULP877A Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

Integrated
Circuit
Systems, Inc.
ICS97UL P 8 77A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866/
SSTUA32864/SSTUA32866/SSTUA32S868/
SSTUA32S865/SSTUA32S869
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667)
• Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667)
• OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667)
• CYCLE - CYCLE jitter 40ps
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
52-Ball BGA
1
A CLKT1
B CLKC1
C CLKC2
D CLKT2
E CLK_INT
F CLK_INC
G AGND
H AVDD
J CLKT3
K CLKC3
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
Top View
3
4
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
5
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
Block Diagram
LD⁽¹⁾ or OE
CLKT0
OE
CLKC0
OS
AVDD
Powerdown
Control and
Test Logic
LD⁽¹⁾, OS, or OE
LD⁽¹⁾
PLL Bypass
CLK_INT
CLK_INC
GND
FB_INT
FB_INC
PLL
NOTE:
1. The Logic Detect (LD) powers down the device when a logic LOW is
applied to both CLK_INT and CLK+INC.
7116—03/27/07
CLKT1
CLKC1
CLKT2
CLKC2
VDDQ
1
CLKC2
2
CLKT3
CLKT2
3
CLKC3
CLK_INT
4
CLK_INC
5
CLKT4
CLKC4
VDDQ
6
AGND
7
CLKT5
CLKC5
AVDD
8
VDDQ
9
CLKT6
GND
10
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
40-Pin MLF
30
CLKC7
29
CLKT7
28
VDDQ
27
FB_INT
26
FB_INC
25
FB_OUTC
24
FB_OUTT
23
VDDQ
22
OE
21
OS