ICS93735 Datasheet, PDF (1/7 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Zero Delay Clock Buffer

Integrated
Circuit
Systems, Inc.
ICS93735
DDR Phase Lock Loop Zero Delay Clock Buffer
Recommended Application:
DDR Zero Delay Clock Buffer
Product Description/Features:
• Low skew, low jitter PLL clock driver
• Max frequency supported = 266MHz (DDR 533)
• I²C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input
Switching Characteristics:
• CYCLE - CYCLE jitter (66MHz): <120ps
• CYCLE - CYCLE jitter (>100MHz): <65ps
• CYCLE - CYCLE jitter (>200MHz): <75ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 500ps - 700ps
• DUTY CYCLE: 49.5% - 50.5%
Functionality
INPUTS
OUTPUTS
AVDD
CLK_INT
CLKT
CLKC FB_OUTT
2.5V (nom)
L
L
H
L
2.5V (nom)
H
H
L
H
2.5V (nom)
< offset freq* offset freq* offset freq* offset freq*
GND
L
L
H
L
GND
H
H
L
H
* The offset frequency is ~ 20 MHz, varying somewhat from part to part.
Block Diagram
Pin Configuration
PLL State
on
on
off
Bypassed/off
Bypassed/off
48-Pin SSOP
SCLK
SDATA
Control
Logic
FB_INT
PLL
CLK_INT
0579E—08/06/03
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9