ICS9150-08 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Pentium/Pro™

Integrated
Circuit
Systems, Inc.
ICS9150- 08
Frequency Generator & Integrated Buffers for Pentium/Pro™
General Description
The ICS9150-08 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are selectable.
Features include three CPU, seven PCI and seventeen SDRAM
clocks. Two reference output is available equal to the crystal
frequency, plus two IOAPIC outputs powered by VDDL1.
One 48 MHz for USB is provided plus a 24 MHz. Spread
Spectrum built in at ±0.5% or ±0.25% modulation to reduce
EMI. Serial programming I²C interface allows changing
functions, stop clock programing and Frequency selection. It
is not recommended to use dual function I/O pins to clock
slots (ISA, PIC, CPU, DIMM). The add on card may have a
pull-up or pull-down. Additionally, the device meets the
Pentium power-up stabilization, which requires that CPU and
PCI clocks be stable within 2ms after power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycle. The REF, 24 and 48 MHz
clock outputs typically provide better than 0.5V/ns slew rates
into 20pF.
Block Diagram
Features
• 3.3V outputs: SDRAM, PCI, REF, 48/24MHz
• 2.5V outputs: CPU, IOAPIC
• 20 ohm CPU clock output impedance
• 20 ohm PCI clock output impedance
• Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center
2.6 ns.
• No external load cap for C_L=18pF crystals
• ±250 ps CPU, PCI clock skew
• 250ps (cycle to cycle) CPU jitter
• Smooth CPU frequency switching from 50 to 133 MHz
• I²C interface for programming
• 2ms power up clock stable time
• Clock duty cycle 45-55%.
• 56 pin 300 mil SSOP package
• 3.3V operation, 5V tolerant inputs (with series R)
• <5.5ns SDRAM propagation delay from Buffer Input
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:18), supply for PLL core,
VDD4 = 48MHz, 24MHz
VDDL1 = IOAPIC_F
VDDL2 = CPUCLK_F (1:2)
9150-08 Rev E 09/28/98
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I²C is a trademark of Philips Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.