ICS9148-47 Datasheet, PDF (1/9 Pages) Integrated Circuit Systems – Pentium/ProTM System Clock Chip

Integrated
Circuit
Systems, Inc.
ICS9148-47
Pentium/Pro^TM System Clock Chip
General Description
The ICS9148-47 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-11 and –12.
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I²C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), seven PCI
(3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz,
and one selectable 48/24MHz.
Features
• Generates system clocks for CPU, PCI, IOAPIC ,
14.314 MHz, 48 and 24MHz.
• Supports single or dual processor systems
• Skew from CPU (earlier) to PCI clock 1 to 4ns
• Separate 2.5V and 3.3V supply pins
• 2.5V outputs: CPU, IOAPIC
• 3.3V outputs: PCI, REF
• No power supply sequence requirements
• 28 pin SOIC
• Spread Sectrum operation optional for PLL1
• CPU frequencies to 100MHz are supported.
Pin Configuration
Block Diagram
9148-47 Rev D 08/04/98
28 pin SOIC
Power Groups
VDD = Supply for PLL core
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = 48MHz
VDDL = CPUCLK (0:1)
VDDL1=IOAPIC
Ground Groups
GND = Ground Source Core
GND1 = REF0, X1, X2
GND2 = PCICLK_F, PCICLK (0:5)
GND3=48MHz
GNDL = CPUCLK (0:1)
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.