ICS91305 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – High Performance Communication Buffer

Integrated
Circuit
Systems, Inc.
ICS91305
High Performance Communication Buffer
General Description
The ICS91305 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with
the CLKOUT signal. It is designed to distribute high speed
clocks in communication systems operating at speeds
from 10 to 133 MHz.
ICS91305 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
Features
• Zero input - output delay
• Frequency range 10 - 133 MHz (3.3V)
• 5V tolerant input REF
• High loop filter bandwidth ideal for Spread
Spectrum applications.
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 pin 150 mil SOIC & 173 mil
TSSOP packages
• 3.3V ±10% operation
The ICS91305 comes in an eight pin 150 mil SOIC
package. It has five output clocks. In the absence of REF
input, will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
Block Diagram
Pin Configuration
REF 1
CLK2 2
CLK1 3
GND 4
8 CLKOUT
7 CLK4
6 VDD
5 CLK3
8 pin SOIC & TSSOP
0092G—08/06/07