ICS9112-28 Datasheet, PDF (1/3 Pages) Integrated Circuit Systems – Low Skew Output Buffer

Integrated
Circuit
Systems, Inc.
ICS9112-28
Preliminary Product Preview
Low Skew Output Buffer
General Description
The ICS9112-28 is a high performance, low skew, low jitter
clock driver. It is designed to distribute high speed clocks in
PC systems operating at speeds from 0 to 133 MHz.
The ICS9112-28 comes in an eight pin 150 mil SOIC package.
It has four output clocks.
Features
• Frequency range 0 - 133 MHz (3.3V)
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 pin 150 mil SOIC &
173 mil TSSOP packages.
• 3.3V ±10% operation
Block Diagram
CLK_IN
CLK0
CLK1
CLK2
CLK3
CLK4
Pin Configuration
CLK_IN 1
CLK0 2
GND 3
CLK1 4
8 CLK4
7 VDD
6 CLK3
5 CLK2
8 pin SOIC
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
PIN NAME
CLK_IN
CLK0¹
GND
CLK1¹
CLK2¹
CLK3¹
VDD
CLK4¹
Notes:
1. Weak pull-down on all outputs
TYPE
IN
OUT
PWR
OUT
OUT
OUT
PWR
OUT
Input reference frequency.
Buffered clock output
Ground
Buffered clock output
Buffered clock output
Buffered clock output
Power Supply (3.3V)
Buffered clock output
DESCRIPTION
9112-28 Rev B 01/09/06
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.