ICS889831 Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS889831 is a high speed 1-to-4 Differential-
ICS
to-LVPECL/ECL Fanout Buffer and is a member
HiPerClockS™ _{of the HiPerClockS™family of high performance}
clock solutions from ICS. The ICS889831 is
optimized for high speed and very low output
skew, making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre
Channel. The internally terminated differential input and
VREF_AC pin allow other differential signal families such as
LVDS, LVHSTL and CML to be easily interfaced to the input
with minimal use of external components.The device also has
an output enable pin which may be useful for system test
and debug purposes. The ICS889831 is packaged in a small
3mm x 3mm 16-pin VFQFN package which makes it ideal
for use in space-constrained applications.
FEATURES
• 4 differential LVPECL/ECL outputs
• IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
•
50Ω
internal
input
termination
to
V
T
• Maximum output frequency: > 2.1GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 185ps (maximum)
• Additive phase jitter, RMS: 0.27ps (typical)
• Propagation delay: 570ps (maximum)
• LVPECL mode operating voltage supply range:
V_CC = 2.5V ± 5%, 3.3V ± 5%, V_EE = 0V
• ECL mode operating voltage supply range:
V_CC = 0V, V_EE = -3.3V ± 5%, 2.5V ± 5%
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
EN
IN ^50Ω
V_T
nIN
50Ω
D
Q
LE
V
REF_AC
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
16 15 14 13
Q1 1
12 IN
nQ1 2
11 VT
Q2 3
1 0 VREF_AC
nQ2 4
9 nIN
5678
Q2
nQ2
ICS889831
16-Lead VFQFN
Q3
3mm x 3mm x 0.95 package body
nQ3
K Package
Top View
889831AK
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 16, 2005