ICS8701I Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8701I is a low skew, ÷1, ÷2 Clock Gen-
,&6
erator and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS out-
W puts are designed to drive 50 series or par-
allel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also con-
trols the active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V in-
put supply, and 2.5V output supply operating modes. Guar-
anteed bank, output and part-to-part skew characteristics
make the ICS8701I ideal for those clock distribution appli-
cations demanding well defined performance and repeat-
ability.
FEATURES
W • 20 LVCMOS outputs, 7 typical output impedance
• Output frequency up to 250MHz
• 200ps bank skew, 250ps output skew, 300ps multiple
frequency skew, 600ps part-to-part skew
• LVCMOS / LVTTL clock input
• LVCMOS control inputs
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
• -40°C to 85°C ambient operating temperature
• Other divide values available on request
BLOCK DIAGRAM
¸1
LVCMOS_CLK
¸2
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
1
QAO - QA4
0
1
QB0 - QB4
0
1
QC0 - QC4
0
1
QD0 - QD4
0
Bank Enable
Logic
PIN ASSIGNMENT
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
7
ICS8701I
31
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23
24
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
48-Pin LQFP
Y Package
Top View
8701I
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 16, 2001