ICS8525 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4
LVCMOS-TO-LVHSTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8525 is a low skew, high performance
,&6
1-to-4 LVCMOS-to-LVHSTL fanout buffer and a
HiPerClockS™ _{member of the HiPerClockS™ family of High}
Performance Clock Solutions from ICS. The
ICS8525 has two selectable clock inputs that ac-
cept LVCMOS or LVTTL input levels and translate them to
1.8V LVHSTL levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8525 ideal for those applications demanding
well defined performance and repeatability.
FEATURES
• 4 differential 1.8V LVHSTL outputs
• Selectable LVCMOS / LVTTL clock inputs for redundant
and multiple frequency fanout applications
• Maximum output frequency up to 266MHz
• Translates LVCMOS and LVTTL levels to 1.8V
LVHSTL levels
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.9ns (maximum)
• 3.3V core, 1.8V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK0
0
CLK1
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
GND 1 20 Q0
CLK_EN 2 19 nQ0
CLK_SEL 3
18 VDDO
CLK0 4 17 Q1
Q0
nc 5 16 nQ1
nQ0
CLK1 6 15 Q2
nc 7 14 nQ2
Q1
nQ1
nc 8
nc 9
13 VDDO
12 Q3
Q2
VDD 10 11 nQ3
nQ2
ICS8525
Q3
20-Lead TSSOP
nQ3
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
8525BG
www.icst.com/products/hiperclocks.html
1
REV. B JULY 27, 2001