ICS844003I-01 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844003I-01 is a 3 differential output LVDS
ICS
Synthesizer designed to generate Ethernet refer-
HiPerClockS™ _{ence clock frequencies and is a member of the}
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequen-
cies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 844003I-01 has 2
output banks, Bank A with 1 differential LVDS output pair and
Bank B with 2 differential LVDS output pairs.
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.56ps (typical)
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies men-
tioned above. The ICS844003I-01 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844003I-01 is packaged in a small
24-pin TSSOP package.
• 3.3V output supply mode
• -40°C to 85°C ambient operating temperature
PIN ASSIGNMENT
BLOCK DIAGRAM
CLK_ENA ^Pullup
DIV_SELA[1:0] ^Pullup
VCO_SEL ^Pullup
TEST_CLK ^Pulldown
0
XTAL_IN
XTAL_OUT
OSC
1
Phase
Detector
VCO
0 0 ÷1
0 1 ÷2
0
1 0 ÷3
1 1 ÷4 (default)
1
DIV_SELB0 1
VCO_SEL 2
MR 3
24 DIV_SELB1
2 3 VDDO_B
22 QB0
VDDO_A 4
QA0 ⁵
nQA0 ⁶
CLK_ENB ⁷
CLK_ENA 8
FB_DIV ⁹
VDDA ^{1 0}
VDD ¹¹
DIV_SELA0 ¹²
21 nQB0
20 QB1
19 nQB1
18 XTAL_SEL
17 TEST_CLK
16 _{XTAL_IN}
15 _{XTAL_OUT}
14 _GND
13 _{DIV_SELA1}
ICS844003I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
QA0
nQA0
XTAL_SEL ^Pullup
FB_DIV ^Pulldown
DIV_SELB[1:0] ^Pullup
MR ^Pulldown
CLK_ENB ^Pullup
FB_DIV
0 = ÷25 (default)
1 = ÷32
0 0 ÷2
0 1 ÷4
1 0 ÷5
1 1 ÷8 (default)
QB0
nQB0
QB1
nQB1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
1