ICS670-04 Datasheet, PDF (1/6 Pages) Integrated Circuit Systems – LOW PHASE NOISE, ZERO DELAY BUFFER AND MULTIPLIER

ICS670-04
LOW PHASE NOISE, ZERO DELAY BUFFER AND MULTIPLIER
Description
The ICS670-04 is a high speed, low phase noise, Zero
Delay Buffer (ZDB) which integrates ICS’ proprietary
analog/digital Phase Locked Loop (PLL) techniques. It
is identical to the ICS670-02, but with an increased
maximum output frequency of 210 MHz. Part of ICS’
ClockBlocks^TM family, the part’s zero delay feature
means that the rising edge of the input clock aligns with
the rising edges of the outputs giving the appearance of
no delay through the device. There are two identical
outputs on the chip. The FBCLK should be used to
connect to the FBIN. Each output has its own output
enable pin.
The ICS670-04 is ideal for synchronizing outputs in a
large variety of systems, from personal computers to
data communications to video. By allowing off-chip
feedback paths, the chip can eliminate the delay
through other devices. The 15 different on-chip
multipliers work in a variety of applications. For other
multipliers, including functional multipliers, see the
ICS527.
Features
• Packaged in 16-pin SOIC Pb (lead) free
• Clock inputs from 5 to 210 MHz (see page 2)
• Patented PLL with low phase noise
• Output clocks up to 210 MHz at 3.3 V
• 15 selectable on-chip multipliers
• Power down mode available
• Low phase noise: -111 dBc/Hz at 10 kHz
• Output enable function tri-states outputs
• Low jitter 15 ps one sigma
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V or 5 V
• Industrial temperature grade
Block Diagram
ICLK
FBIN
Divide by
N
VDD
3
Phase
Detector,
Charge
Pump, and
Loop Filter
OE1
Voltage
Controlled
Oscillator
S3:S0
4
3
GND
External Feedback from FBCLK is recommended.
OE2
FBCLK
CLK2
MDS 670-04 B
1
Revision 011905
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