ICS670-01 Datasheet, PDF (1/5 Pages) Integrated Circuit Systems – Low Phase Noise Zero Delay Buffer and Multiplier

ICS670-01
Low Phase Noise Zero Delay Buffer and Multiplier
Description
Features
The ICS670-01 is a high speed, low phase noise
Zero Delay Buffer (ZDB) which integrates ICS’
proprietary analog/digital Phase Locked Loop
(PLL) techniques. Part of ICS’ ClockBlocks™
family, the zero delay feature means that the rising
edge of the input clock aligns with the rising edges
of the outputs, giving the appearance of no delay
through the device. There are two identical outputs
on the chip. The FBCLK should be used to
connect to the FBIN. Each output has its own
output enable pin.
The chip is ideal for synchronizing outputs in a
large variety of systems, from personal computers
to data communications to video. By allowing off-
chip feedback paths, the ICS670-01 can eliminate
the delay through other devices. The 15 different
on-chip multipliers work in a variety of
applications. For other multipliers, including
fractional multipliers, see the ICS527.
• Packaged in 16 pin SOIC
• Clock inputs from 5 to 160 MHz (see page 2)
• Patented PLL with the lowest phase noise
• Output clocks up to 160 MHz at 3.3 V
• 15 selectable on-chip multipliers
• Power down mode available
• Low phase noise: -124 dBc/Hz at 10 kHz
• Output Enable function tri-states outputs
• Low jitter 15 ps one sigma
• Full swing CMOS outputs with 25 mA drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• Industrial temperature version available
• 3.3 V or 5 V operation
Block Diagram
ICLK
FBIN
S3:S0
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
4
ROM-
Based
Multipliers
OE1
Output
Buffer
Output
Buffer
External feedback from FBCLK is recommended.
OE2
FBCLK
CLK2
MDS 670-01 B
1
Revision 100900
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126•[phone]tel•http://www.icst.com