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9DBV0541 Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – HCSL compatible differential input | |||
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5 O/P 1.8V PCIe Gen1-2-3 Fan-out Buffer
w/Zo=100ohms
9DBV0541
DATASHEET
Description
The 9DBV0541 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. It has integrated terminations for direct
connection to 100ohm transmission lines. The device has 5
output enables for clock management, and 3 selectable
SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
⢠5 â 1-200MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100ï
Key Specifications
⢠DIF additive cycle-to-cycle jitter <5ps
⢠DIF output-to-output skew < 50ps
⢠DIF additive phase jitter is <100fs rms for PCIe Gen3
⢠DIF additive phase jitter <300fs rms for SGMII
Features/Benefits
⢠Integrated terminations; save 36 resistors compared to
standard HCSL outputs
⢠50mW typical power consumption; minimal power
consumption
⢠OE# pins; support DIF power management
⢠HCSL compatible differential input; can be driven by
common clock sources
⢠Programmable Slew rate for each output; allows tuning for
various line lengths
⢠Programmable output amplitude; allows tuning for various
application environments
⢠1MHz to 200MHz operating frequency
⢠3.3V tolerant SMBus interface works with legacy controllers
⢠Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
⢠Device contains default configuration; SMBus interface not
required for device operation
⢠Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Block Diagram
vOE(4:0)#
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
5
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0541 REVISION B 08/28/14
1
©2014 Integrated Device Technology, Inc.
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