9DBV0531 Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – 1MHz to 200MHz operating frequency

5 O/P 1.8V PCIe Gen1-2-3 Fan-out Buffer
9DBV0531
DATASHEET
Description
The 9DBV0531 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 5 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
• 5 - 1-200MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
• DIF additive cycle-to-cycle jitter <5ps
• DIF output-to-output skew < 50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms for SGMII
Features/Benefits
• LP-HCSL outputs; save 10 resistors compared to standard
HCSL outputs
• 45mW typical power consumption; minimal power
consumption
• OE# pin for each output; support DIF power management
• HCSL differential input; can be driven by common clock
sources
• Spread Spectrum tolerant; allows reduction of EMI
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• 1MHz to 200MHz operating frequency
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Device contains default configuration; SMBus interface not
required for device operation
• Space saving 40-pin 5x5mm VFQFPN; minimal board
space
Block Diagram
vOE(4:0)#
5
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0531 REVISION C 08/28/14
1
©2014 Integrated Device Technology, Inc.