9DB433 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – SMBus Interface; unused outputs can be disabled

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
DATASHEET
9DB433
General Description
The 9DB433 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB433 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Recommended Application
4 output PCIe Gen1,2,3 zero-delay/fanout buffer
Key Specifications
• Output cycle-cycle jitter <50ps
• Output to Output skew <50ps
• Phase jitter: PCIe Gen3 <1.0ps rms
Functional Block Diagram
2
OE(6,1)#
Features/Benefits
• 3 Selectable SMBus Addresses; Mulitple devices can
share the same SMBus Segment
• OE# pins; Suitable for Express Card applications
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible; tracks spreading input
clock for low EMI
• SMBus Interface; unused outputs can be disabled
• Supports undriven differential outputs in Power Down
mode for power management
Output Features
• 4 - 0.7V current-mode differential HCSL output pairs
• Supports zero delay buffer mode and fanout mode
• Selectable bandwidth
• 50-110 MHz operation in PLL mode
• 5-166 MHz operation in Bypass mode
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
4
STOP
LOGIC
DIF(6,5,2,1)
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
1
9DB433
REV G 08/25/15