IC41C16257 Datasheet, PDF (9/20 Pages) Integrated Circuit Solution Inc – 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
AC CHARACTERISTICS^{(1,2,3,4,5,6)}
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
-35
Min. Max.
tACH Column-Address Setup Time to CAS
Precharge during WRITE Cycle
tOEH OE Hold Time from WE during
READ-MODIFY-WRITE cycle⁽¹⁸⁾
tDS
Data-In Setup Time^{(15, 22)}
tDH
Data-In Hold Time^{(15, 22)}
tRWC READ-MODIFY-WRITE Cycle Time
tRWD RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle⁽¹⁴⁾
tCWD CAS to WE Delay Time^{(14, 20)}
tAWD Column-Address to WE Delay Time⁽¹⁴⁾
15 —
8—
0—
6—
80 —
45 —
25 —
30 —
tPC
tRASP
tCPA
tPRWC
tOFF
tCLCH
tCSR
tCHR
tORD
Fast Page Mode READ or WRITE
12
Cycle Time⁽²⁴⁾
Fast Page Mode RAS Pulse Width
35
Access Time from CAS Precharge⁽¹⁵⁾
—
Fast Page Mode READ-WRITE Cycle Time⁽²⁴⁾ 40
Output Buffer Turn-Off Delay from
3
CAS or RAS^{(13,15,19, 29)}
Last CAS going LOW to First CAS
10
returning HIGH⁽²³⁾
CAS Setup Time (CBR REFRESH)^{(30, 20)}
8
CAS Hold Time (CBR REFRESH)^{(30, 21)}
8
OE Setup Time prior to RAS during
0
HIDDEN REFRESH Cycle
—
100K
21
—
15
—
—
—
—
tREF Refresh Period (512 Cycles)
tT
Transition Time (Rise or Fall)^{(2, 3)}
—8
1 50
-50
Min. Max.
15 —
10 —
0—
8—
125 —
70 —
34 —
42 —
20 —
50 100K
— 27
47 —
3 15
10 —
10 —
10 —
0—
—8
1 50
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
-60
Min. Max. Units
15 —
ns
15 —
ns
0—
ns
10 —
ns
140 —
ns
80 —
ns
36 —
ns
49 —
ns
25 —
ns
60 100K ns
— 34
ns
56 —
ns
3 15
ns
10 —
ns
10 —
ns
10 —
ns
0—
ns
—8
ms
1 50
ns
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
9
DR021-0A 08/11/2001