IC89LV52 Datasheet, PDF (8/22 Pages) Integrated Circuit Solution Inc – CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 8(4)-Kbytes of FLASH

IC89LV52(51)A
Flash Command Definitions
Normal Verify₍₁₎
Read Signature Byte
Program Code Memory
Program Verify₍₁₎
Program Lock Bit 1
Program Lock Bit 2
Program Lock Bit 3
Chip Erase
Erase Verify₍₁₎
Bus
Cycle
(n+1)
(2)
4
2
(n+1) ₍₂₎
2
2
2
2
(n+1) ₍₂₎
First Bus Cycle
Operation Address Data
P2.6
X
00H
P2.6
X
90H
VPP
H
H
P2.6
P2.6
P2.6
P2.6
P2.6
P2.6
P2.6
X
40H H
X
C0H H
X
60H H
X
70H H
X
80H H
X
20H H
X
A0H H
Second Bus Cycle
Operation Address Data
VPP
P2.7 Low SA
SD
H
(3)
(3)
P2.7 Low 30H D5H
31H 52H
PROG
P2.7 Low
PROG
PROG
PROG
PROG
32H
PA
(3)
SA
X
X
X
X
55H/AAH
PD
(3)
PVD₍₃₎
D0H
12V/H
H
12V/H
D0H 12V/H
D0H 12V/H
D0H 12V/H
P2.7 Low
EA₍₃₎
EVD₍₃₎
H
Note:
1. Normal Verify: Internal flash sense amplifier uses the same threshold as instruction executing threshold.
Program Verify: The flash sense amplifier applies an internally generated higher margin
voltage to the addressed byte. If a comparison between the programmed byte and the true data is successful, there
is a margin exists in the programmed data.
Erase Verify: The flash sense amplifier applies an internally generated lower margin voltage to the addressed
byte. Reading FFH from the addressed byte indicates that all bits in the bytes are erased.
2. To verify n bytes data.
3. SA = Selected Address of memory location to be read except program or erase verify.
SD = Data read from location SA with Normal Verification threshold.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
PVD = Data read from location PA during program verify.
EA = Address of memory location to be read during erase verify.
EVD - Data read from location EA during erase verify.
Programming Core Memory
Every code byte in the Flash array can be written and the entire array can be erased using the appropriate command
from Port 0 by programmer or application system. The program/erase are two-cycle operations. The first cycle is command
write cycle; the command 40H is written by P2.6 falling and rising edges. The command would be held a stable value within
P2.6 low state. The command decoder enables programming flag after the first cycle is completion, then the internal
programming flag is set. Rising edge of PROG will clear internal programming flag, so the programming command must
be presented every programming cycle. The second cycle is real flash programming cycle. The programming address and
data are latched at PROG falling edge, the programming time is controlled by low time of PROG. The programming flag
is cleared at PROG rising edge in the second cycle. Programming address range is from 0 to 1FFFH. IC89LV52(51)A
programming range is from 0 to 1FFFH, but the program counter will jump to external menory while MCU executing the
address is excess 0FFFH.
The IC89LV52(51)A code memory programming now is described in Figure 6.
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Integrated Circuit Solution Inc.
MC010-0D 11/16/2001