IC89C54 Datasheet, PDF (8/24 Pages) Integrated Circuit Solution Inc – CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 16/32/64-Kbytes of FLASH

IC89C54/58/64
The IC89C54/58/64 provide the user with a direct flash
memory access that can be used for programming into the
flash memory without using the CPU. The direct flash
memory access is entered using the External Host Mode.
While the reset input (RST) is continually held active (high),
if the PSEN pin is forced by an input with low state, the
device enters the External Host Mode arming state at this
time. The CPU core is stopped from running and all the chip
I/O pins are reassigned and become flash memory access
and control pins. At this time, the external host should
initiate a “Read Signature Bytes” operation. After the
completion of the “Read Signature Bytes” operation, the
device is armed and enters the External Host Mode. After
the device enters into the External Host Mode, the internal
flash memory blocks are accessed through the re-assigned
I/O port pins by an external host, such as a printed circuit
board tester, a PC controlled development board or an
MCU programmer.
When the chip is in the external host mode, Port 0 pins
are assigned to be the parallel data input and output pins.
Port 1 pins are assigned to be the low order address bus
signals for the internal flash memory (A0-A7). The first six
bits of Port 2 pins (P2[0:5]) are assigned to be the upper
order address bus signals for the internal flash memory
(A8-A13) along with two of the Port 3 pins (P3.2 as A14 and
P3.3 as A15). Two upper order Port 2 pins (P2.6 and P2.
7) and two upper order Port 3 pins (P3.6 and P3.7) along
with RST, PSEN, PROG/ALE, EA pins are assigned as the
control signal pins. The P3.4 is assigned to be the ready/
busy status signal, the P3.5 is assigned to be the timeout
A7-A0
A13-A8
A15-A14
P1
P2.5-2.0
P3.3-3.2
signal, which can be used for handshaking with the external
host during a flash memory programming operation. The
flash memory programming operation (Erase, Program,
Verify, etc.) is internally self-timed and can be controlled by
an external host asynchronously or synchronously.
The insertion of an “arming” command prior to entering
the External Host Mode by utilizing the “Read Signature
Bytes” operation provides additional protection for
inadvertent writes to the internal flash memory cause by a
noisy or unstable system environment during the power-up
or power unstable conditions.
The External Host Mode uses hardware setup mode,
which are decoded from the control signal pins, to facilitate
the internal flash memory erase, test and programming
process. The External Host Mode Commands are enabled
on the falling edge of ALE/PROG. The list in Table 3
outlines all the setup conditions of normal mode. Before
entering these written modes must have read 3 signature
bytes.
Programming Interface
Some conditions must be satisfied before entering the
programming mode. The conditions are listed in table 3.
The interface-controlled signals are matched these
conditions, then the IC89C54/58/64 will enter received
command mode. The flash command is accepted by the
flash command decoder in command received mode. The
programming interface is listed in figure 6.
VCC
P0
VCC
10K
D7-D0
H
L
PROG pulse
12V/H
RST
PSEN
ALE/PROG
EA/VPP
VSS
P3.4
P3.5
P2.6
P2.7
P3.6
P3.7
Ready/Busy
Timeout
P2.6
P2.7
P3.6
P3.7
Figure 6. IC89C52/54/64 External Host Programming Signals
8
Integrated Circuit Solution Inc.
MC009-0B