IC62LV5128L Datasheet, PDF (8/11 Pages) Integrated Circuit Solution Inc – 512Kx8 bit Low Voltage and Ultra Low Power CMOS Static RAM

IC62LV5128L
IC62LV5128LL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range, Standard and Low Power)
Symbol Parameter
-55
-70
-100
Min. Max.
Min. Max.
Min. Max
Unit
tWC Write Cycle Time
tSCE CE to Write End
55 —
70 —
100 —
ns
50 —
65 —
80 —
ns
tAW Address Setup Time to Write End
50 —
65 —
80 —
ns
tHA
Address Hold from Write End
0—
0—
0—
ns
tSA
Address Setup Time
tPWE WE Pulse Width
0—
0—
0—
ns
40 —
40 —
80 —
ns
tSD
Data Setup to Write End
25 —
30 —
40 —
ns
tHD
tHZWE⁽³⁾
tLZWE⁽³⁾
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0—
0—
0—
ns
— 30
— 30
— 40
ns
5—
5—
5—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in
Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled)
ADDRESS
CE
WE
DOUT
DIN
tWC
tSCE
tHA
tAW
tPWE
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
8
Integrated Circuit Solution Inc.
LPSR012-0B 08/31/2001