IC41C4105 Datasheet, PDF (8/17 Pages) Integrated Circuit Solution Inc – 1Mx4 bit Dynamic RAM with Fast Page Mode

IC41C4105 and IC41LV4105
AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tOFF
tCSR
tCHR
tORD
tREF
tT
Parameter
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle⁽¹⁸⁾
Data-In Setup Time^{(15, 22)}
Data-In Hold Time^{(15, 22)}
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle⁽¹⁴⁾
CAS to WE Delay Time^{(14, 20)}
Column-Address to WE Delay Time⁽¹⁴⁾
Fast Page Mode READ or WRITE
Cycle Time
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge⁽¹⁵⁾
Fast Page Mode READ-WRITE Cycle Time
Output Buffer Turn-Off Delay from
CAS or RAS^{(13,15,19, 24)}
CAS Setup Time (CBR REFRESH)^{(20, 25)}
CAS Hold Time (CBR REFRESH)^{( 21, 25)}
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Auto Refresh Period 1,024 Cycles
Transition Time (Rise or Fall)^{(2, 3)}
-35
Min. Max.
15
−
8
−
0
−
6
−
80
−
45
−
25
−
30
−
12
−
35 100K
-
21
40
−
3
15
8
−
8
−
0
−
−
16
1
15
-50
Min. Max.
15 −
-60
Min. Max.
15
−
10 − 15
−
0
−
0
−
8
− 10
−
125 − 140 −
70 − 80
−
34 − 36
−
42 − 49
−
20 − 25
−
50 100K 60
-
27
-
47 − 56
3 15 3
100K
34
−
15
10 − 10
−
10 − 10
−
0
−
0
−
− 16 −
16
1 50 1
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V + 10%)
One TTL Load and 50 pF (Vcc = 3.3V + 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.4V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
8
Integrated Circuit Solution Inc.
DR019-0A 08/01/2001