IC62C1024 Datasheet, PDF (7/8 Pages) Integrated Circuit Solution Inc – 128K X 8 HIGH SPEED CMOS STATIC RAM

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WRITE CYCLE NO. 2 (+-, CE2 Controlled)^(1,2)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
CE LOW
WE
DOUT
t SA
DATA UNDEFINED
t AW
t PWE1
t HZWE
DIN
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Circuit Solution Inc.
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ALSR005-0A