IC41C82052S Datasheet, PDF (7/18 Pages) Integrated Circuit Solution Inc – 2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

IC41C82052S
IC41LV82052S
AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tO..
tWHZ
tCSR
tCHR
tORD
tRE.
Parameter
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODI.Y-WRITE cycle⁽¹⁸⁾
Data-In Setup Time^{(15, 22)}
Data-In Hold Time^{(15, 22)}
READ-MODI.Y-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODI.Y-WRITE Cycle⁽¹⁴⁾
CAS to WE Delay Time^{(14, 20)}
Column-Address to WE Delay Time⁽¹⁴⁾
EDO Page Mode READ or WRITE
Cycle Time
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge⁽¹⁵⁾
EDO Page Mode READ-WRITE
Cycle Time
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS^{(13,15,19, 24)}
Output Disable Delay from WE
CAS Setup Time (CBR RE.RESH)^{(20, 25)}
CAS Hold Time (CBR RE.RESH)^{( 21, 25)}
OE Setup Time prior to RAS during
HIDDEN RE.RESH Cycle
Auto Refresh Period
2,048 Cycles
-50
Min. Max.
15 —
8
—
0
—
8
—
108 —
64 —
26 —
39 —
20 —
50 100K
— 30
56 —
5
—
0
12
3
10
5
—
8
—
0
—
— 32
tRE.
Self Refresh Period
2,048 Cycles — 128
tT
Transition Time (Rise or .all)^{(2, 3)}
1 50
1
-60
Min. Max.
15 —
10 —
0
—
10 —
133 —
77 —
32 —
47 —
25 —
60 100K
— 35
68 —
5
—
0
15
3
10
5
—
10 —
0
—
— 32
— 128
50 ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 p. (Vcc = 5.0V + 10%)
One TTL Load and 50 p. (Vcc = 3.3V + 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Integrated Circuit Solution Inc.
7
DR016-0A 06/12/2001