IS61LV5128 Datasheet, PDF (6/8 Pages) Integrated Circuit Solution Inc – 512K x 8 HIGH-SPEED CMOS STATIC RAM

IS61LV5128
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
tWC Write Cycle Time
tSCE CE to Write End
tAW Address Setup Time
to Write End
tHA Address Hold from Write End
tSA Address Setup Time
tPWE WE Pulse Width
tSD Data Setup to Write End
tHD Data Hold from Write End
tHZWE WE LOW to High-Z Output
tLZWE WE HIGH to Low-Z Output
-8
Min. Max.
8—
7—
7—
0—
0—
7—
4.5 —
0—
—4
3—
-10
Min. Max.
10 —
8—
8—
0—
0—
8—
5—
0—
—5
3—
-12
Min. Max.
12 —
9—
9—
0—
0—
9—
6—
0—
—6
3—
-15
Min. Max. Unit
15 — ns
10 — ns
10 — ns
0 — ns
0 — ns
10 — ns
7 — ns
0 — ns
— 7 ns
3 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1^{ (1,2 )}(CE Controlled, OE is HIGH or LOW)
ADDRESS
CE
WE
DOUT
DIN
t WC
VALID ADDRESS
t SA
t SCE
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
6
Integrated Circuit Solution, Inc.
SR027-0C