IC62VV12816L Datasheet, PDF (6/11 Pages) Integrated Circuit Solution Inc – 128Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM

IC62VV12816L
IC62VV12816LL
IC62VV12816LL POWER SUPPLY CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
ICC1 Vcc Dynamic Operating
Supply Current
ICC2 Vcc Dynamic Operating
Supply Current
Test Conditions
VCC = 1.8V, CE ≤ VIL
IOUT = 0 mA, f = fMAX
VCC = 1.8V, CE ≤ VIL
IOUT = 0 mA, f = 1MHZ
-70
-100
Typ⁽²⁾. Max. Typ⁽²⁾. Max. Unit
Com.
7 15
4 10 mA
Ind.
7 15
4 10
Com.
—2
— 2 mA
Ind.
—2
—2
ISB2
CMOS Standby
VCC = Max., Other inputs= 0 - VCC
Com.
Current (CMOS Inputs) 1) CE ≥ VCC – 0.2V (CE controlled)
Ind.
2) LB/ UB ≥ VCC – 0.2V (LB/ UB controlled)
0.5 5
— 10
0.5 5
µA
— 10
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vcc=1.8V, Ta=25°C, and are not guaranteed or tested.
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-70
-100
Min. Max.
Min. Max.
Unit
tRC
Read Cycle Time
70 —
100 —
ns
tAA
Address Access Time
— 70
— 100
ns
tOHA
tACE
tDOE
tHZOE⁽²⁾
tLZOE⁽²⁾
tHZCE⁽²⁾
tLZCE⁽²⁾
tBA
tHZB
tLZB
Output Hold Time
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB o High-Z Output
LB. UB to Low-Z Output
10 —
— 70
— 35
— 25
5—
0 25
10 —
— 70
0 25
0—
15 —
ns
— 100
ns
— 50
ns
— 30
ns
5—
ns
0 30
ns
10 —
ns
— 100
ns
0 35
ns
0—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output
loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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Integrated Circuit Solution Inc.
LPSR024-0A 4/23/2002